Early PA-RISC Processors

The very first PA-RISC processors designed by HP following the Precision Architecture were used in mid- to late-1980s early HP 9000 800 servers. These 32-bit RISC processors implemented PA-RISC 1.0 in multi-chip designs with separate chips for the central processing unit, contrary to the mostly single-chip post-PA-7000 processors from the 1990s.

CPU	Details	Year
TS-1	First PA-RISC, six boards TTL	1986
NS-1	NMOS, single board, single CPU	1987
NS-2	NMOS, single board, CPU + 7 chips	1989
PCX	CMOS, single CPU, Stirling	1990

Early PA-RISC CPUs were first based on TTL manufacturing, then NMOS-III and finally CMOS26B. HP’s PA-RISC 1.0 designs had clock speeds from 8 MHz up to 50 MHz in later versions, with 128 to 512 MB main memory. System designs were mostly based on the System Main Bus (SMB), as used in the early HP 9000 800 servers.

Naming is not always coherent as some sources refers to the processors as TS-1, NS-1, NS-2 and PCX while others call the same processors PN-5, PN-7, PN-10, CMOS26b. Generally, sources and documentation on these pre-Internet PA-RISC processors is rather sparse to non-existent, adding to the slight unclearities.

TS-1 PA-RISC Processor

TS-1 was the very first PA-RISC production processor from HP, introduced in 1986. It implemented version 1.0 of PA-RISC on six 8.4×11.3″ boards of TTL and was used in the first PA-RISC computers shipped by HP.

TS-1 were used in HP 9000 840 servers with several boards for processing units, processor pipeline, a 4096-entry TLB and 128 KB L1 cache, divided into 64 KB for each data and instruction. The TTL boards measured 8.4×11.3″ with SRAMs/PALs and about 150 ICs each. HP moved to NMOS in the next CPUs before settling on CMOS later in the 1990s.

Details

PA-RISC version 1.0 32-bit, three-stage pipeline
The CPU consists of six separate boards:
1. I-unit Instruction Unit
2. Register File Board, contains general and control registers
3. E-unit Execution Unit
4. TLB translation lookaside buffer with 4096 entries for 2 KB pages
5. Cache controller with split instruction and data caches of 64 KB each
6. FPC floating-point coprocessor, handles FP operations parallel to the CPU/ALU
  the NMOS-III ADD/MUL/DIV chips were taken over from FOCUS
TLB off-chip, direct-mapped, 4096 entries
Cache 128 KB offchip L1 direct-mapped/one-way associative
Physical address space of 27-bit, 128 MB main memory could be addressed
Clock speed 8 MHz
Six or five printed circuit boards, implemented in FAST TTL and 25ns/35ns SRAMs/PALs, with each about 150 ICs
Pictures of TS-1 CPU boards at Computermuseum University Stuttgart

Used in

HP 9000 840 servers, the first PA-RISC computers.

NS-1 PA-RISC Processor

HP NS-1 processors were the first implementation of PA-RISC 1.0 in a NMOS fabrication process, released in 1987 shortly after the original TTL-based TS-1. HP NS-1 PA-RISC processors were integrated on a single circuit board (two on 825 servers). The CPU was a single NMOS-III chip supplemented by several external support chips.

Details

PA-RISC version 1.0 32-bit, three-stage pipeline
Single CPU with eight support VLSI chips
1. SIU system interface unit attaches the CPU to the SMB main bus
2. CCU cache controller units CCU0 and CCU1 attach to external cache
3. TCU TLB controller unit attaches to the external TLB
4. MIU math interface unit with three third-party FP chips ADD, MUL and DIV
  FP chips were the same as in TS-1 on the HP 9000 840, taken from FOCUS
TLB off-chip with 2048 to 4096 entries
L1 cache 16 KB to 128 KB, unified and off-chip
Physical address space of 29-bit, 512 MB main memory could be addressed
CPU attaches via System Main Bus SMB to memory and I/O controllers, 64-bit bus
Clock speed 25-30 MHz
One circuit board, two boards on HP 9000 825
115,000 FETs, implemented in NMOS-III 1.5µ, die size 8.4×8.4 mm² in a 272-pin ceramic PGA package

Used in

HP 9000 825, 834, 835, 850 servers

NS-2 PA-RISC Processor

The final HP NMOS PA-RISC processor was NS-2, a tweaked follow-on to the NS-1, introduced in 1989-90. NS-2 increased pipeline stages from three to five, had new TLB and cache controllers and significantly larger caches and TLB.

The NS-2 is implemented on one circuit board with the CPU as a single NMOS-III and seven other VLSI chips. The bus structure connecting these chips was updated and simplified, with the CPU having private connections to the cache and TLB controllers, for which the NS-1 CPU had to use the shared cache bus.

Details

PA-RISC version 1.0 32-bit, five-stage pipeline
CPU is a single chip with seven VLSI support chips
1. SIU system interface unit, attaches the CPU to the SMB main bus
2. CCU cache controller units ICCU and DCCU, attach to external cache chips
3. TCU TLB controller unit, attaches to external TLB chips
4. FPC floating point controller and two third-party FP chips ADD, MULTI
TLB off-chip, 16384 entries
Cache up to 1024 KB L1, split into instruction and data, off-chip
Physical address space of 29-bit, 512 MB main memory could be addressed
CPU attaches via System Main Bus SMB to memory and I/O controllers, synchronous, pipelined 64-bit bus
Clock speed 27.5 or 30 MHz, power dissipation of 26W
One circuit board, CPU implemented in 1.5µ NMOS-III, 183,000 FETs, die size 14.0×14.0 mm² die, packaged in 408-pin PGA

Used in

PCX (CMOS26B) PA-RISC Processor

PCX (Chimera) was the last PA-RISC 1.0 processor, introduced 1990 and the first PA-RISC processor fabricated in a CMOS process. It implemented the PA-RISC NS-1/NS-2 design and several of the processor functions previously supplied on external VLSI chips onto a single CPU chip. PCX was possibly the HP Stirling processor and/or the CS-1.

PCX was supplemented by external support chips, including three cache multiplexers, SPI main bus to processor interface, floating point coprocessor and two FP chips for MUL/DIV and ADD/SUB. PCX was the first PA-RISC multiprocessing capable CPU.

PA-RISC version 1.0 32-bit
First multi-processor-capable PA-RISC CPU, up to four-way SMP (realized in 870S)
Seven external supported chips
External FPU (apparently ECL logic)
TLB on-chip with 8192 entries with second-level TLB
Cache up to 1 MB L1, split into instruction and data, off-chip, asymmetrical 1:2, some systems used up to 4 MB (890)
Cache two-way set associative
Physical address space of 29-bit, 512 MB main memory could be addressed
CPU attaches via System Main Bus SMB to memory and I/O controllers, 64-bit bus
Clock speed up to 50 MHz or 60 MHz (some sources mentioned 90 MHz)
One circuit board, 196,000 FETs, 1.0µ (micron), implemented in three-level CMOS26B, packaged in 408-pin multilayer PGA
Seven VLSI support chips for memory/bus interfaces and I/O

The successor to PCX was the PA-RISC 1.1 PCX-S processor (or PA-7000), which integrated most processor logic minus the FPU onto a single die/chip.

Used in

HP 9000 808, 815 servers
HP 9000 842, 852, 865, 870 servers
HP 9000 890 enterprise servers

Note: Some sources mention a CS-1 PA-RISC 1.0 processor — CS would point to CMOS design but performance figures and diagrams do not really match up with the CMOS26B or PCX. Other sources describe an evolution of the last PA-RISC 1.0 CPU in CMOS – with up to 60 MHz (90 MHz), 4 MB L1 cache and PMB interface in a 408-pin PGA with 1.4×1.4cm die and 479k transistors – which in turn is eerily close to the PA-7000 processor.

Documentation

Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture (January 1988: Software Research Northwest Inc.)
Hardware Design of the First HP Precision Architecture Computers (PDF) David A. Fotland et al (March 1987: Hewlett-Packard Journal) hp museum
HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook (PDF) Hewlett-Packard Company (October 1990. Accessed January 2008) hp museum
HP 9000 Series 800 Model 825S Hardware Technical Data (PDF) Hewlett-Packard Company (September 1988. Accessed January 2008) hp museum
HP 3000/925 and HP 9000 825/835 Computer Systems CE Handbook (PDF) Hewlett-Packard Company (May 1988. Accessed January 2008) hp museum
New midrange members of the Hewlett-Packard Precision Architecture Computer Family Thomas O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at findarticles.com)
HP 9000 Series 800 Model 822S/832S Technical Data (PDF) Hewlett-Packard Company (1989. Accessed January 2008) hp museum
A 30 MIPS VLSI CPU, Brian D. Boschma et al (ISSCC 89: February 1989)
A CMOS RISC CPU designed for sustained high performance on large applications, J. Lotz et al (IEEE Journal of Solid-State Circuits October 1990)
A 90 MHz CMOS RISC CPU designed for sustained performance, D. Tanksalvala et al (1990 37th IEEE International Conference on Solid-State Circuits)
HP systems & vlsi technology division: pa-risc abstracts archive.org, Hewlett-Packard Company (2002)