Advertisement
National Semiconductor Corp.'s chief executive Brian Halla at the Microprocessor Forum in San Jose yesterday outlined Cyrix Corp.'s roadmap, which shows the introduction next year of a MediaPC microprocessor running at 233 to 300 MHz for the ultra-low-cost PC market.
Cyrix's MediaPC is a low-cost system-on-a-chip, which integrates a microprocessor, video decompression engine, 2D graphics, and associated peripheral logic, aimed at an evolving sector of the PC market that Halla expects will be priced “free.” [See story National’s Halla predicts PCs will be free within a year]
Slightly more expensive will be the MXi, based upon the Cayenne core that Cyrix will be shipping shortly. Cayenne adds a second MMX unit to the Cyrix's M II design, as well as the 3Dnow! multimedia instructions developed by AMD and Cyrix.
Advertisement
The MXi will add a 3D graphics core when it ships in April 1999, according to Michael Slater, president of Sebastopol, Calif.-based analyst firm MicroDesign Resources Inc. The chip will run at 333 MHz to over 400 MHz, Halla said.
Advertisement
Finally, Halla confirmed EBN's earlier report that National will still pursue the Socket 7 market with “Jedi,” an MXi style processor family designed for Socket 7.
While Halla presented Jedi as a separate chip, Jedi is actually a separate program within Cyrix that will apply the Cayenne core “cost-effectively to the Socket 7 market,” said Stan Swearingen, vice-president of PC products for Cyrix based in Richardson, Texas.
Swearingen disclosed that Jedi will be a Socket 7 chip; he did not comment on whether Jedi would be manufactured in the “Socket 370” PGA package that Intel has disclosed as part of a socket-based Pentium II processor using the P6 bus.
Beyond the Jedi family, National will introduce in the year 2000 its next-generation core code-named “Jalapeno,” which will be marketed as the “M3” chip
Jalapeno will be designed as a discrete chip running at speeds exceeding 600 MHz and manufactured on a 0.18-micron process.
As a discrete chip, Jalapeno will feature a dual-issue architecture, with register renaming and out-of-order execution, according to Greg Grohoski, an engineer with Cyrix. The chip will integrate 256 kilobytes of level 2 cache directly on the die. To minimize the need to access both the level 1 and level 2 cache, Cyrix has designed in a Rambus memory interface directly onto the die.
The M3 will combine 3D graphics and the Jalapeno core beginning in the fourth quarter of 1999, Grohoski said. The M3's 3D graphics engine should process up to 3 million polygons per second, 266 million pixels per second using a 233 MHz clock, he said. The M3 uses the level 2 cache to store textures, and will include standard features like fog, alpha blending, and bi- and tri-linear filtering.
0 comments on “Microprocessor Forum: Cyrix spices up PC with Jalapeno”