vhdl
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Revisit CLI syntax
Currently, the architecture of the CLI is based on (sub)commands and options. Commands are expected to be provided as the first argument, and do effectively decide which feature is to be used. OTOH, options provide parameters to the commands. However, there is no syntactical difference, as both commands and options start with -- or -i. As a result, we rely on properly formating --help and on
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Apr 1, 2022 - Haskell
#23 was closed, and a follow on action was to document how to configure the cocotb logger to separate it and the simulator stdout.
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Apr 2, 2022 - VHDL
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Jan 3, 2022
Here is the problem:
$ make compile
Traceback (most recent call last):
File "C:\My_Designs\probe_fpga_design_1\run.py", line 336, in
main()
File "C:\My_Designs\probe_fpga_design_1\run.py", line 181, in main
vu.add_osvvm()
File "c:\my_designs\probe_fpga_design_1\deps\vunit\vunit\ui_init_.py", line 1030, in add_osvvm
self.builtins.add("osvvm")
File "c:\my
Currently we don't reset registers or we use := initalisers when defining signals.
This works ok in FPGAs and ghdl sim but sucks for ASIC and gate level sim as it causes a lot of X state propagation issues.
Scrub all of the code to add resets to register state.
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Nov 29, 2020 - VHDL
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Apr 1, 2022 - Python
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Jan 5, 2019 - VHDL
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Nov 10, 2021
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Nov 23, 2021 - VHDL
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Mar 27, 2022 - C++
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Mar 30, 2022 - VHDL
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Sep 22, 2020 - C++
Create NeoVim integration of VHDL language server and publish instructions on how to use it.
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My school uses the DE0 and the DE0-CV interchangeably, so one day I may need to use one and another day need to use another. Logisim-evolution supports the DE0, and supports other Cyclone V based FPGAs, but not specifically the DE0-CV.