Anne Meixner

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Anne Meixner is a contributing editor at Semiconductor Engineering. She has 30+ years in the semiconductor industry. She became fascinated by defects in the semiconductor manufacturing process as a young engineer at IBM. Over that period, she has focused on test methodology with emphasis on mixed-signal and analog DFT and test. As a technical communicator she takes complex ideas and explains them in consumable understandable pieces. Meixner has worked at IBM, Carnegie Mellon University and Intel. She holds three U.S. patents and her peers have recognized her work with two best papers at IEEE International Test Conference. She founded The Engineers’ Daughter in 2015 to consult on semiconductor testing and to coach engineers.

Author's Latest Posts

HBM Shifts Testing Left To Preserve AI Chip Yield
By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

Untrusted Analog Components Add Risks For Critical Infrastructure
By Anne Meixner - 07 Apr, 2026 - Comments: 0

Key Takeaways New certificate-based solutions are necessary within fabs and packaging houses to deliver trusted semiconductors. Physical IDs bind the device to the certificate, but it needs to be immutable and unclonable. Extrinsic IDs are required for analog, mixed-signal, sensor ICs as well as discrete components. Rising concern over the source and destination of chips, an... » read more

Chiplets Add More Inspection And Test Steps
By Anne Meixner - 10 Feb, 2026 - Comments: 0

Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Zero-Trust Data Sharing Architectures Redefining Chip Manufacturing
By Anne Meixner - 09 Dec, 2025 - Comments: 0

Real-time security clearances are becoming increasingly common in the manufacturing of advanced-node semiconductors, where data sharing is both essential and a potential security threat. Data security is a well-known issue in semiconductor manufacturing, but much of it is based on an outdated approach. In its place, zero-trust architectures [1] are now a requirement for new equipment and ins... » read more

New Rules Put The Squeeze On Semiconductor Gray Market
By Anne Meixner - 11 Nov, 2025 - Comments: 0

The shift toward chiplets and multi-die assemblies is forcing big changes in the global supply chain, including much tighter cooperation between companies and governments to ensure the authenticity and quality of semiconductor parts. The chip industry has been looking to digital certificates as the best means of reducing counterfeiting and ensuring consistent quality for some time. The probl... » read more

Hybrid Approach Emerges For Edge/Cloud Inspection Of Chips
By Anne Meixner - 14 Oct, 2025 - Comments: 0

An explosion in data from inspection images and metrology measurements is creating a confusing set of demands for chipmakers and their equipment vendors. On one hand they need the massive storage and compute resources of the cloud to utilize AI/ML-based models, but they also need the faster response time of the edge to make adjustments at the tool level. Balancing these requirements is a mas... » read more

Infusing Trust Into The Supply Chain
By Anne Meixner - 09 Sep, 2025 - Comments: 0

An expanding supply chain of dies feeding multi-die products is prompting chipmakers to reassess and expand on ways to instill trust from end to end. This reaches deeper than just connecting disparate data. It requires integrating complex systems across vendors and protecting vendor data while instilling confidence in their customers and partners. Yet despite the time and effort that has bee... » read more

Chiplet Interfaces Embrace Failures
By Anne Meixner - 12 Aug, 2025 - Comments: 0

Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen. For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-f... » read more

Detecting Slips, Scratches, Cracks In Wafers And Dies Becoming Harder
By Anne Meixner - 10 Jul, 2025 - Comments: 0

Defect detection requirements on the order of 10 defective parts per million (DPPM) are driving improvements in inspection tools’ resolution and throughput at foundries and OSATs. However, defects that manifest as slips, scratches, and micro-cracks continue to bedevil the prevalent optical inspection methods. These defects can range in size from nanometers to millimeters, some of which are... » read more

High-Quality Data Needed To Better Utilize Fab Data Streams
By Anne Meixner - 10 Jun, 2025 - Comments: 0

Fab operations have wrestled with big data management issues for decades. Standards help, but only if sufficient attention to detail is taken during collection. Semiconductor wafer manufacturing represents one of the most complex manufacturing processes in the world. With each generation of process improvement comes more sophisticated fab equipment, new process recipes, and exponential incre... » read more

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