Uncore
 | This article needs to be updated. (January 2017) |
"Uncore" is a term used by Intel to describe the functions of a microprocessor that are not in the core, but which must be closely connected to the core to achieve high performance. It was introduced with the Nehalem microarchitecture.[1] It has been called "system agent" since the release of the Sandy Bridge microarchitecture.[2]
The Uncore/SA handles the functionalities traditionally assigned to the northbridge: QPI controllers, L3 cache, snoop agent pipeline, on-die memory controller, on-die PCI Express Root Complex, and Thunderbolt controller.[3] Integration of these functions into the core makes them physically closer, thereby reducing their access latency. In contrast, the "core" (processor) component consists of the control unit, ALU, FPU, and L1 and L2 caches.[4] Other bus controllers such as SPI and LPC are part of the chipset (Platform Controller Hub), the equivalent of the southbridge.[4] Further integration has since eliminated the PCH from the motherboard for a system-in-package design on mobile SKUs.[5]
Parts
[edit]Specifically, the microarchitecture of the Nehalem-EX uncore is broken down into a number of modular units. The main uncore interface to the core is the so-called cache box (CBox), which interfaces with the last level cache (LLC) and is responsible for managing cache coherency. Multiple internal and external QPI links are managed by physical-layer units, referred to as PBox. Connections between the PBox, CBox, and one or more iMCs (MBox) are managed by the system configuration controller (UBox) and a router (RBox).[6]
Removal of serial bus controllers from the Intel uncore further enables increased performance by allowing the uncore clock (UCLK) to run at a base of 2.66 GHz, with overclocking limits in excess of 3.44 GHz.[7] This increased clock rate allows the core to access critical functions (such as the IMC) with significantly less latency, typically reducing core access times to DRAM by 10 ns or more.
References
[edit]- ^ "Ultrabook, SmartPhone, Laptop, Desktop, Server, & Embedded– Intel". Intel.com. Retrieved 2014-01-21.
- ^ Anand Lal Shimpi (September 14, 2010). "Intel's Sandy Bridge Architecture Exposed". AnandTech. Archived from the original on September 16, 2010. Retrieved July 15, 2015.
- ^ "Thunderbolt™ Technology for Developers". Intel.com. 2014-01-13. Retrieved 2014-01-21.
- ^ a b "Nehalem: The Unwritten Chapters". AnandTech. Archived from the original on June 1, 2009. Retrieved 2014-01-21.
- ^ Cutress, Ian. "Intel Releases Broadwell-U: New SKUs, up to 48 EUs and Iris 6100". www.anandtech.com. Archived from the original on January 7, 2015.
- ^ "Intel(R) Xeon(R) Processor 7500 Series Uncore Programming Guide" (PDF). Retrieved 2014-01-30.
- ^ Yus, Carlos (2011-01-27). "HighPerformanceSystems: Intel Sandy Bridge out of specification 4.0, 4.4 and 4.6 GHz. Updated – HighPerformanceSystems". Highperformancesystems.blogspot.com. Retrieved 2014-01-21.
Also remember that in this test Nehalem has a Uncore and L3 cache frequency increased to 3.44 GHz from 2.66 GHz nominal, which helps greatly.
Additional references
[edit]"Thunderbolt™ Technology for Developers." Intel.com. Retrieved March 30, 2025.
Anand Lal Shimpi, "Intel's Sandy Bridge Architecture Exposed," AnandTech, September 14, 2010; updated information available in later reviews of later architectures.
"Intel® Xeon® Processor Uncore Programming Guide." Intel.com. Retrieved March 2025.